So for ring counters, a mod 4 ring counter means it has four flip-flops and four states. It is an important label for a counter because it gives us the maximum count of the counter, as well as the number of flip-flops present in the counter. As the count depends on the clock signal, in case of an Asynchronous counter, changing state bits are provided as the clock signal to the subsequent flip-flops. Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs). But remember that we are counting 0 too, so to count ten events, we need to actually count up to 9 and not 10. We will be using the D flip-flop to design this counter. Now question is how can we do that? Counter is the widest application of flip-flops. How to design a 4-bit synchronous down counter and 4-bit synchronous up-down counter? We will now design the truth table for this counter. We can mathematically represent a mod n counter as. MOD-4 Counter State Diagram We can see from the truth table of the counter, and by reading the values of QA and QB, when QA = 0 and QB = 0, the count is 00. The only difference is that instead of attaching the non-inverted outputs to the display port, we will attach the inverted outputs. It has a series of flip-flops connected together. The configuration made in such a way that the counter will reset itself to zero at a pre-configured value and has truncated sequences. My implementation consistis of using a control variable ctrl so when it's 0, the counter counts in ascendant order, else in descendent one.. thanks for sharing this..i got more explanation about counter, with simple explanation,,it is very useful for starters.. We know we are going to have four flip-flops. The design remains the same. Thus the counter will count from 0000 to 1001. This type of counters called as Decade Counters. Counters are of two types. It could count 16 events or from 0-15 decimals. If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a counter is called as synchronous counter. Here is a logic circuit of a 4-bit ring counter. Asynchronous 4-bit DOWN counter. The NAND gate output is zero when the count reaches 10 (1010). So the display would start with displaying 1, 2, 3 and then 0. The below image is showing the timing diagram and the 4 outputs status on the clock signal. We will be using the D flip-flop to design this counter. This will give us the decade counter. And the high bit of the first flip-flop moves to the second flip-flop. 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